Abstract

Silicon is the material of choice for fabrication of high circuit density, low defect density and high speed integrated devices. CMOS technology provides the additional advantage of low power dissipation. These features make CMOS technology an attractive candidate to take advantage of the performance enhancements available through liquid nitrogen temperature operation. However, low temperature operation may increase the hot carrier generation of both substrate and gate currents -- which can degrade device performance and reliability.

This dissertation begins briefly with an overview of the advances and drawbacks of cryogenic device operation. The focus then shifts to hot carrier effects, since they prove detrimental to operation at both normal and cryogenic temperatures. In particular, characterization of the temperature, channel length, and voltage dependences of the weak avalanche substrate current between 77K and 300K will be presented. A microscopic, physical model based on Shockley's lucky electron approach will be described which explains this impact ionization behavior. The model incorporates a Maxwell-Boltzmann distribution of hot carrier energies beyond the band minima, and is implemented in the 2D device simulators CADDET and PISCES. Specific tools have been developed in PISCES for analyzing hot carrier effects, using the results of this model.

Device gate current in short-channel NMOS FET's is also characterized at low temperatures and realistic biases. The measurements have implications for gate current modeling, device reliability, and reliability modeling. These implications are discussed in detail, and specific, quantitative suggestions are made on the necessary attributes for a 2D gate current model.

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